Numerical recipes in C: the art of scientific computing
Numerical recipes in C: the art of scientific computing
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improving the efficiency of power simulators by input vector compaction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Stochastic sequential machine synthesis targeting constrained sequence generation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Stratified random sampling for power estimation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A novel methodology for transistor-level power estimation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Sequence compaction for probabilistic analysis of finite-state machines
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical sequence compaction for power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Accurate power estimation for large sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast power estimation for deterministic input streams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast Transforms: Algorithms, Analyses, Applications
Fast Transforms: Algorithms, Analyses, Applications
Monte-Carlo Approach for Power Estimation in Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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In this paper, we present a power estimation technique for control-flow intensive designs that is tailored towards driving iterative high-level synthesis systems, where hundreds of architectural trade-offs are explored and compared. Our method is fast and relatively accurate. The algorithm utilizes the behavioral information to extract branch probabilities, and uses these in conjunction with switching activity and circuit capacitance information, to estimate the power consumption of a given architecture.We test our algorithm using a series of experiments, each geared towards measuring a different indicator. The first set of experiments measures the algorithm's accuracy when compared to the actual circuit power. The second set of experiments measures the average tracking index, and tracking index fidelity for a series of architectures. This index measures how well the algorithm makes decisions when comparing the relative power consumption of two architectures contending as low-power candidates.Results indicate that our algorithm achieved an average estimation error of 11.8% and an average tracking index of 0.95 over all examples.