Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
Improving the efficiency of power simulators by input vector compaction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Learning belief networks from data: an information theory based approach
CIKM '97 Proceedings of the sixth international conference on Information and knowledge management
Stream synthesis for efficient power simulation based on spectral transforms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Probabilistic Networks and Expert Systems
Probabilistic Networks and Expert Systems
Vector Compaction for Efficient Simulation-Based Power Estimation
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Learning Bayesian Networks
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequence compaction for power estimation: theory and practice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
Binary Decision Diagrams and neural networks
The Journal of Supercomputing
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
Expert Systems with Applications: An International Journal
Binary decision diagrams: a mathematical model for the path-related objective functions
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Investigating data preprocessing methods for circuit complexity models
Expert Systems with Applications: An International Journal
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A trace compression algorithm targeting power estimation of long benchmarks
Proceedings of the International Conference on Computer-Aided Design
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Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active leakage power, coupling noises in CMOS implementations. In this work, we model the input-space by a causal graphical probabilistic model that encapsulates the dependencies in inputs in a compact, minimal fashion and also allows for instantiations of the vector-space that closely match the underlying dependencies, with the constraint that the reduced vector-space captures the dependencies in the larger dataset accu-rately. Results on ISCAS benchmark show that average error is limited to 1.8% while we achieve a compaction ratio of 300.