Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the Optimal Variable Ordering for Binary Decision Diagrams
IEEE Transactions on Computers
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Efficient variable ordering using aBDD based sampling
Proceedings of the 37th Annual Design Automation Conference
The multiple variable order problem for binary decision diagrams: theory and practical application
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using lower bounds during dynamic BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Binary Decision Diagrams and neural networks
The Journal of Supercomputing
Binary decision diagrams: a mathematical model for the path-related objective functions
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
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This paper describes a new mathematical model for the estimation of reduced ordered binary decision diagram's (ROBDD's) complexity, for any Boolean function with different degrees of variables complexity. The model is capable of predicting the maximum possible ROBDD complexity for Boolean functions with given number of variables. The proposed model is also capable of predicting the number of product terms in the Boolean function that will correspond to the maximum complexity of the ROBDD. This mathematical model works for any type of variable reordering method, and will enable the system performance to be analyzed without building the ROBDD. Since ROBDD complexity can be predicted without building it, a great reduction in terms of time complexity for VLSI CAD designs can be achieved and very useful clues to tackle ROBDD optimization problems in the design of digital circuits can also be obtained.