Digital logic testing and simulation
Digital logic testing and simulation
Future paths for integer programming and links to artificial intelligence
Computers and Operations Research - Special issue: Applications of integer programming
Annals of Operations Research - Special issue on Tabu search
Signal and image processing with neural networks: a C++ sourcebook
Signal and image processing with neural networks: a C++ sourcebook
Circuit complexity and neural networks
Circuit complexity and neural networks
Discrete neural computation: a theoretical foundation
Discrete neural computation: a theoretical foundation
Binary decision diagram with minimum expected path length
Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A neural network algorithm for the traveling salesman problem with backhauls
Computers and Industrial Engineering - Special issue: Focussed issue on applied meta-heuristics
Neural Networks for Combinatorial Optimization: a Review of More Than a Decade of Research
INFORMS Journal on Computing
A two-stage simulated annealing methodology
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
Binary Decision Diagrams and neural networks
The Journal of Supercomputing
On places suitable for applying AI principles in NP-hard graph problems' algorithms
AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
IEEE Transactions on Computers
A markov chain framework for the simple genetic algorithm
Evolutionary Computation
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Role of function complexity and network size in the generalization ability of feedforward networks
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing the number of paths in BDDs: Theory and algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Measuring the complexity of functions that represent digital circuits in non-uniform computation models is an important area of computer science theory. This paper presents a comprehensive set of machine learnt models for predicting the complexity properties of circuits represented by binary decision diagrams. The models are created using Monte Carlo data for a wide range of circuit inputs and number of minterms. The models predict number of nodes as representations of circuit size/area and path lengths: average path length, longest path length, and shortest path length. The models have been validated using an arbitrarily-chosen subset of ISCAS-85 and MCNC-91 benchmark circuits. The models yield reasonably low RMS errors for predictions, so they can be used to estimate complexity metrics of circuits without having to synthesize them.