High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2002 international symposium on Low power electronics and design
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Automated fixed-point data-type optimization tool for signal processing and communication systems
Proceedings of the 41st annual Design Automation Conference
High-level area and power-up current estimation considering rich cell library
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
Expert Systems with Applications: An International Journal
Area and power consumption estimations at system level with SystemQ 2.0
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
End-to-end validation of architectural power models
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
Empirical method based on neural networks for analog power modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-fidelity Markovian power model for protocols
Proceedings of the Conference on Design, Automation and Test in Europe
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High-level power estimation, when given only a high-level design specification such as a functional or register-transfer level (RTL) description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the “area complexity” of multi-output combinational logic given only their functional description, i.e., Boolean equations, where area complexity refers to the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the multi-output Boolean function description into an equivalent single output function. The area model is empirical and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented