FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
Convex Optimization
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Custom-optimized multiplierless implementations of DSP algorithms
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimum wordlength search using sensitivity information
EURASIP Journal on Applied Signal Processing
Design and implementation of numerical linear algebra algorithms on fixed point DSPs
EURASIP Journal on Advances in Signal Processing
Proceedings of the 45th annual Design Automation Conference
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Towards program optimization through automated analysis of numerical precision
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Journal of Signal Processing Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
Proceedings of the International Conference on Computer-Aided Design
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems
Proceedings of the Conference on Design, Automation and Test in Europe
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A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point data types of arithmetic operators, including overflow modes, integer word lengths, fractional word lengths, and the number systems. The approach is based on statistical modeling, hardware resource estimation and global optimization based on an initial structural system description. The basic technique exploits the fact that the fixed point realization is a weak perturbation of the floating point realization which allows the development of a system model which can be used in the optimization process.