Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
Proceedings of the conference on Design, automation and test in Europe
FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
Statistical Digital Signal Processing and Modeling
Statistical Digital Signal Processing and Modeling
Accuracy Sensitive Word--Length Selection for Algorithm Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
Automated fixed-point data-type optimization tool for signal processing and communication systems
Proceedings of the 41st annual Design Automation Conference
Closed-form and real-time wordlength adaptation
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
IEEE Transactions on Signal Processing
Simulation-based word-length optimization method for fixed-pointdigital signal processing systems
IEEE Transactions on Signal Processing
Fixed broadband wireless access: state of the art, challenges, and future directions
IEEE Communications Magazine
Analog-to-digital converters and their applications in radio receivers
IEEE Communications Magazine
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wordlength optimization for linear digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and implementation of numerical linear algebra algorithms on fixed point DSPs
EURASIP Journal on Advances in Signal Processing
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Many digital signal processing algorithms are first developed in floating point and later converted into fixed point for digital hardware implementation. During this conversion, more than 50% of the design time may be spent for complex designs, and optimum wordlengths are searched by trading off hardware complexity for arithmetic precision at system outputs. We propose a fast algorithm for searching for an optimum wordlength. This algorithm uses sensitivity information of hardware complexity and system output error with respect to the signal wordlengths, while other approaches use only one of the two sensitivities. This paper presents various optimization methods, and compares sensitivity search methods. Wordlength design case studies for a wireless demodulator show that the proposed method can find an optimum solution in one fourth of the time that the local search method takes. In addition, the optimum wordlength searched by the proposed method yields 30% lower hardware implementation costs than the sequential search method in wireless demodulators. Case studies demonstrate the proposed method is robust for searching for the optimum wordlength in a nonconvex space.