Code generation for compiled bit-true simulation for DSP application
Proceedings of the 11th international symposium on System synthesis
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Bit-Width Selection for Data-Path Implementations
Proceedings of the 12th international symposium on System synthesis
SystemC
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
Proceedings of the 41st annual Design Automation Conference
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Précis: A Usercentric Word-Length Optimization Tool
IEEE Design & Test
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Rapid prototyping of field programmable gate array-based discrete cosine transform approximations
EURASIP Journal on Applied Signal Processing
Optimum wordlength search using sensitivity information
EURASIP Journal on Applied Signal Processing
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A java simulation tool for fixed-point system design
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
Software designs of image processing tasks with incremental refinement of computation
IEEE Transactions on Image Processing
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A real-time FPGA-based 20 000-word speech recognizer with optimized DRAM access
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Journal of Signal Processing Systems
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
EURASIP Journal on Embedded Systems
A bit too precise? bounded verification of quantized digital filters
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 35.69 |
Word-length optimization and scaling software that utilizes the fixed-point simulation results using realistic input signal samples is developed for the application to general, including nonlinear and time-varying, signal processing systems. Word-length optimization is conducted to minimize the hardware implementation cost while satisfying a fixed-point performance measure. In order to minimize the computing time, signal grouping and efficient search methods are developed. The search algorithms first determine the minimum bound of the word-length for an individual group of signals and then try to find out the cost-optimal solution by using either exhaustive or heuristic methods