Rapid prototyping of field programmable gate array-based discrete cosine transform approximations

Authors:
Trevor W. Fox;Laurence E. Turner
Affiliations:
Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada
Venue:
EURASIP Journal on Applied Signal Processing
Year:
2003

Citing 7
Cited 0

Introduction to data compression (2nd ed.)

Introduction to data compression (2nd ed.)
Heuristic datapath allocation for multiple wordlength systems

Proceedings of the conference on Design, automation and test in Europe
Digit-Serial Computation

Digit-Serial Computation
The Theory of Discrete Lagrange Multipliers for Nonlinear Discrete Optimization

CP '99 Proceedings of the 5th International Conference on Principles and Practice of Constraint Programming
Accuracy Sensitive Word--Length Selection for Algorithm Optimization

ICCD '98 Proceedings of the International Conference on Computer Design
Simulation-based word-length optimization method for fixed-pointdigital signal processing systems

IEEE Transactions on Signal Processing
Fast multiplierless approximations of the DCT with the liftingscheme

IEEE Transactions on Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values and datapath wordlengths. Previous DCT design methods can only control the quality of the DCT approximation and estimates of the hardware cost by optimizing the coefficient values. It is shown that it is possible to rapidly prototype FPGA-based DCT approximations with near optimal coding gains that satisfy the MSE, hardware cost, quantization noise, and power consumption specifications.