Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Enhanced Parallel Processing in Wide Registers
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Custom-optimized multiplierless implementations of DSP algorithms
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Pattern Recognition Letters
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Rapid prototyping of field programmable gate array-based discrete cosine transform approximations
EURASIP Journal on Applied Signal Processing
Multiplierless implementation of rotators and FFTs
EURASIP Journal on Applied Signal Processing
Fixed word size implementation of lifting schemes
EURASIP Journal on Applied Signal Processing
Scaled AAN for fixed-point multiplier-free IDCT
EURASIP Journal on Advances in Signal Processing
Reversible resampling of integer signals
IEEE Transactions on Signal Processing
Efficient block-based frequency domain wavelet transform implementations
IEEE Transactions on Image Processing
Implementation of video player for embedded systems
SIP '07 Proceedings of the Ninth IASTED International Conference on Signal and Image Processing
Directional lapped transforms for image coding
IEEE Transactions on Image Processing
Direction-adaptive partitioned block transform for color image coding
IEEE Transactions on Image Processing
Integer DCT based on direct-lifting of DCT-IDCT for lossless-to-lossy image coding
IEEE Transactions on Image Processing
Fast mode dependent directional transform via butterfly-style transform and integer lifting steps
Journal of Visual Communication and Image Representation
Low power hardware-based image compression solution for wireless camera sensor networks
Computer Standards & Interfaces
A multimedia service implementation using MJPEG and QCELP in wireless handset
HSI'05 Proceedings of the 3rd international conference on Human Society@Internet: web and Communication Technologies and Internet-Related Social Issues
N point DCT VLSI architecture for emerging HEVC standard
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Multimedia Tools and Applications
Low-complexity 8-point DCT approximations based on integer functions
Signal Processing
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We present the design, implementation, and application of several families of fast multiplierless approximations of the discrete cosine transform (DCT) with the lifting scheme called the binDCT. These binDCT families are derived from Chen's (1977) and Loeffler's (1989) plane rotation-based factorizations of the DCT matrix, respectively, and the design approach can also be applied to a DCT of arbitrary size. Two design approaches are presented. In the first method, an optimization program is defined, and the multiplierless transform is obtained by approximating its solution with dyadic values. In the second method, a general lifting-based scaled DCT structure is obtained, and the analytical values of all lifting parameters are derived, enabling dyadic approximations with different accuracies. Therefore, the binDCT can be tuned to cover the gap between the Walsh-Hadamard transform and the DCT. The corresponding two-dimensional (2-D) binDCT allows a 16-bit implementation, enables lossless compression, and maintains satisfactory compatibility with the floating-point DCT. The performance of the binDCT in JPEG, H.263+, and lossless compression is also demonstrated