Orthogonal Transforms for Digital Signal Processing
Orthogonal Transforms for Digital Signal Processing
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations
Journal of VLSI Signal Processing Systems
Unified Matrix Treatment of the Fast Walsh-Hadamard Transform
IEEE Transactions on Computers
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
Microprocessors & Microsystems
Fast multiplierless approximations of the DCT with the liftingscheme
IEEE Transactions on Signal Processing
A refined fast 2-D discrete cosine transform algorithm with regular butterfly structure
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
High Performance, Low Complexity Video Coding and the Emerging HEVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
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This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 32 × 32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.