Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Authors:
Sergio Saponara;Maurizio Martina;Michele Casula;Luca Fanucci;Guido Masera
Affiliations:
Department of Information Engineering, University of Pisa, via Caruso 16, I-56122 Pisa, Italy;Department of Electronics, Politecnico di Torino, C.so Duca degli Abruzzi 24, I-1029 Torino, Italy;Department of Information Engineering, University of Pisa, via Caruso 16, I-56122 Pisa, Italy;Department of Information Engineering, University of Pisa, via Caruso 16, I-56122 Pisa, Italy;Department of Electronics, Politecnico di Torino, C.so Duca degli Abruzzi 24, I-1029 Torino, Italy
Venue:
Microprocessors & Microsystems
Year:
2010

Citing 20
Cited 5

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Networks on Chips: A New SoC Paradigm

Computer
UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC

IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Fast motion estimation within the H.264 codec

ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 3 (ICME '03) - Volume 03
Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems

IEICE - Transactions on Information and Systems
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance and complexity co-evaluation of the advanced video coding standard for cost-effective multimedia communications

EURASIP Journal on Applied Signal Processing
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

IEEE Transactions on Computers
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Evaluating SoC Network Performance in MPEG-4 Encoder

Journal of Signal Processing Systems
Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accelerating CABAC encoding for multi-standard media with configurability

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Dynamic control of motion estimation search parameters for low complex H.264 video coding

IEEE Transactions on Consumer Electronics
Efficient pipelined CABAC encoding architecture

IEEE Transactions on Consumer Electronics
Hardware architecture design of video compression for multimedia communication systems

IEEE Communications Magazine
A flexible parallel architecture adapted to block-matching motion-estimation algorithms

IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard

IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

IEEE Transactions on Circuits and Systems for Video Technology
High-Throughput Architecture for H.264/AVC CABAC Compression System

IEEE Transactions on Circuits and Systems for Video Technology

Computation and power reduction techniques for H.264 intra prediction

Microprocessors & Microsystems
N point DCT VLSI architecture for emerging HEVC standard

VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing

VLSI Design
A multi-processor NoC-based architecture for real-time image/video enhancement

Journal of Real-Time Image Processing
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720x480 video sequences at 30 frames/s and grant more than 50Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip).