Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
Communication Architectures for System-on-Chip
Proceedings of the 14th symposium on Integrated circuits and systems design
A Case Study in Networks-on-Chip Design for Embedded Video
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
Scalable MPEG-4 encoder on FPGA multiprocessor SOC
EURASIP Journal on Embedded Systems
Evaluating large system-on-chip on multi-FPGA platform
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
Microprocessors & Microsystems
| Hi-index | 0.00 |
This paper shows how a bus topology performs as a System-on-Chip (SoC) interconnection. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The studied MPSoC contains up to 22 IP blocks: 11 soft processors, 8 hardware accelerators and three other components. A novel approach of frequency scaling is used to isolate the impact of various architecture components. The system is benchmarked in various configurations. For example, HIBI is run at 100脳 speed with respect to processors to resemble ideal interconnection. Based on the measurements with up to 16.9frames/s CIF (352 脳 288) encoding speed, estimation for HDTV resolution video encoder is presented. The required optimizations are discussed. Finally, it is shown that 25frames/s 1280 脳 720 video encoder needs 55 MHz HIBI but 670 MHz general-purpose soft RISC processors. In practice, the processing performance has to be boosted by implementing hardware acceleration and improving memory hierarchy. Clearly, HIBI is not the limiting factor.