Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads

Authors:
Rikard Thid;Ingo Sander;Axel Jantsch
Affiliations:
Royal Institute of Technoogy, Sweden;Royal Institute of Technoogy, Sweden;Royal Institute of Technoogy, Sweden
Venue:
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Year:
2006

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Abstract

We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a NoC and a bus based platform are analyzed.