Annals of Operations Research - Special issue on Tabu search
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
Journal of Parallel and Distributed Computing
Mapping and Scheduling for Architecture Exploration of Networking SoCs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Automated memory-aware application distribution for Multi-processor System-on-Chips
Journal of Systems Architecture: the EUROMICRO Journal
Parameter-optimized simulated annealing for application mapping on networks-on-chip
LION'12 Proceedings of the 6th international conference on Learning and Intelligent Optimization
Design space pruning through hybrid analysis in system-level design space exploration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting domain knowledge in system-level MPSoC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
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Mapping an application on Multiprocessor System-on-Chip (MPSoC) is a crucial step in architecture exploration. The problem is to minimize optimization effort and application execution time. Simulated annealing (SA) is a versatile algorithm for hard optimization problems, such as task distribution on MPSoCs. We propose an improved automatic parameter selection method for SA to save optimization effort. The method determines a proper annealing schedule and transition probabilities for SA, which makes the algorithm scalable with respect to application and platform size. Applications are modeled as Kahn Process Networks (KPNs). The method was improved to optimize KPNs and save optimization effort by doing sensitivity analysis for processes. The method is validated by mapping 16 to 256 node KPNs onto an MPSoC. We optimized 150 KPNs for 3 architectures. The method saves over half the optimization time and loses only 0.3% in performance to non-automated SA. Results are compared to non-automated SA, Group migration, random mapping and brute force algorithms. Global optimum solution are obtained by brute force and compared to our heuristics. Global optimum convergence for KPNs has not been reported before. We show that 35% of optimization runs reach within 5% of the global optimum. In one of the selected problems global optimum is reached in as many as 37% of optimization runs. Results show large variations between KPNs generated with different parameters. Cyclic graphs are found to be harder to parallelize than acyclic graphs.