Automated memory-aware application distribution for Multi-processor System-on-Chips

  • Authors:

  • Heikki Orsila;Tero Kangas;Erno Salminen;Timo D. Hämäläinen;Marko Hännikäinen

  • Affiliations:

  • Tampere University of Technology, Institute of Digital and Computer Systems, PO Box 553, FIN-33101 Tampere, Finland;Nokia Technology Platforms, Visiokatu 6, 33720 Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, PO Box 553, FIN-33101 Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, PO Box 553, FIN-33101 Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, PO Box 553, FIN-33101 Tampere, Finland

  • Venue:
  • Journal of Systems Architecture: the EUROMICRO Journal
  • Year:
  • 2007

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Abstract

Mapping of applications on a Multi-processor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formulated as finding solutions to a cost function of the algorithm performing mapping and scheduling under strict constraints. Our solution is based on simultaneous optimization of execution time and memory consumption whereas traditional methods only concentrate on execution time. Applications are modeled as static acyclic task graphs that are mapped on MP-SoC with customized simulated annealing. The automated mapping in this paper is especially purposed for MP-SoC architecture exploration, which typically requires a large number of trials without human interaction. For this reason, a new parameter selection scheme for simulated annealing is proposed that sets task mapping specific optimization parameters automatically. The scheme bounds optimization iterations to a reasonable limit and defines an annealing schedule that scales up with application and architecture complexity. The presented parameter selection scheme compared to extensive optimization achieves 90% goodness in results with only 5% optimization time, which helps large-scale architecture exploration where optimization time is important. The optimization procedure is analyzed with simulated annealing, group migration and random mapping algorithms using test graphs from the Standard Task Graph Set. Simulated annealing is found better than other algorithms in terms of both optimization time and the result. Simultaneous time and memory optimization method with simulated annealing is shown to speed up execution by 63% without memory buffer size increase. As a comparison, optimizing only execution time yields 112% speedup, but also increases memory buffers by 49%.