Annals of Operations Research - Special issue on Tabu search
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Proceedings of the 6th international workshop on Hardware/software codesign
IEEE Transactions on Parallel and Distributed Systems
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
(R) FAST: A Low-Complexity Algorithm for Efficient Scheduling of DAGs on Parallel Processors
ICPP '96 Proceedings of the Proceedings of the 1996 International Conference on Parallel Processing - Volume 2
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated memory-aware application distribution for Multi-processor System-on-Chips
Journal of Systems Architecture: the EUROMICRO Journal
Fault-aware communication mapping for NoCs with guaranteed latency
International Journal of Parallel Programming
ACM Transactions on Embedded Computing Systems (TECS)
Parameterizing simulated annealing for distributing Kahn process networks on multiprocessor SoCs
SOC'09 Proceedings of the 11th international conference on System-on-chip
| Hi-index | 0.00 |
This paper describes two different approaches to optimizethe performance of SoC architectures in the architectureexploration phase. Both solve the problem to map andschedule a task graph on a target architecture under specialconsideration of on-chip communications. A constructivealgorithm is presented that extends previous work bytaking into account potential data transfers in the future.The second approach is a recursive procedure that is basedon local search techniques in a specially defined neighborhoodof the critical path. Simulated annealing and tabusearch are used as search algorithms. Both approaches findsolutions with better performance than established methodologies.The recursive technique leads to superior resultsthan the constructive approach, however, is limited to smalland mid-sized problems, whereas the constructive algorithmis not limited by this issue.