Synthesis of application-specific multiprocessor systems including memory components
Journal of VLSI Signal Processing Systems - Special issue on application specific array processors (ASAP-92)
Embedded system synthesis by timing constraints solving
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Proceedings of the 6th international workshop on Hardware/software codesign
Proceedings of the 11th international symposium on System synthesis
Embedded system synthesis under memory constraints
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Integrated resource assignment and scheduling of task graphs using finite domain constraints
DATE '99 Proceedings of the conference on Design, automation and test in Europe
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System
EDTC '96 Proceedings of the 1996 European conference on Design and Test
System level memory optimization for hardware-software co-design
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Partial task assignment of task graphs under heterogeneous resource constraints
Proceedings of the 40th annual Design Automation Conference
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code-Size Minimization in Multiprocessor Real-Time Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 2 - Volume 03
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automated memory-aware application distribution for Multi-processor System-on-Chips
Journal of Systems Architecture: the EUROMICRO Journal
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
CP '08 Proceedings of the 14th international conference on Principles and Practice of Constraint Programming
Optimized on-chip pipelining of memory-intensive computations on the cell BE
ACM SIGARCH Computer Architecture News
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Hi-index | 0.00 |
This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which is a part of the prototype system MATAS. The algorithm is well suited for image and video processing applications which have hard memory constraints as well as constraints on cost, execution time, and resource usage. Our algorithm takes into account code and data memory constraints together with the other constraints. It can create pipelined implementations. The algorithm finds a task assignment, a schedule, and data and code memory placement in memory. Infeasible solutions caused by memory fragmentation are avoided. The experiments show that our memory-aware algorithm reduces memory utilization comparing to greedy scheduling algorithm which has time minimization objective. Moreover, memory-aware algorithm is able to find task assignment and schedule when time minimization algorithm fails. MATAS can create pipelined implementations, therefore the design throughput is increased.