A filtering algorithm for constraints of difference in CSPs
AAAI '94 Proceedings of the twelfth national conference on Artificial intelligence (vol. 1)
MILP based task mapping for heterogeneous multiprocessor systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Embedded system synthesis by timing constraints solving
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
Scheduling of conditional process graphs for the synthesis of embedded systems
Proceedings of the conference on Design, automation and test in Europe
A constructive algorithm for memory-aware task assignment and scheduling
Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Constraint-Based Scheduling
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Hybrid Benders Decomposition Algorithms in Constraint Logic Programming
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Algorithms for Hybrid MILP/CP Models for a Class of Optimization Problems
INFORMS Journal on Computing
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An integrated hardware/software approach for run-time scratchpad management
Proceedings of the 41st annual Design Automation Conference
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Hardware/software co-synthesis with memory hierarchies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized on-chip pipelining of memory-intensive computations on the cell BE
ACM SIGARCH Computer Architecture News
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation and calibration of compositional performance analysis models for multi-processor systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Robust non-preemptive hard real-time scheduling for clustered multicore platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip
ACM Transactions on Embedded Computing Systems (TECS)
Maximum-throughput mapping of SDFGs on multi-core SoC platforms
Journal of Parallel and Distributed Computing
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The problem of allocating and scheduling precedence-constrained tasks on the processors of a distributed real-time system is NP-hard. As such, it has been traditionally tackled by means of heuristics, which provide only approximate or near-optimal solutions. This paper proposes a complete allocation and scheduling framework, and deploys an MPSoC virtual platform to validate the accuracy of modelling assumptions. The optimizer implements an efficient and exact approach to the mapping problem based on a decomposition strategy. The allocation subproblem is solved through Integer Programming (IP) while the scheduling one through Constraint Programming (CP). The two solvers interact by means of an iterative procedure which has been proven to converge to the optimal solution. Experimental results show significant speed-ups w.r.t. pure IP and CP exact solution strategies as well as high accuracy with respect to cycle-accurate functional simulation. Two case studies further demonstrate the practical viability of our framework for real-life applications.