Benchmarking mesh and hierarchical bus networks in system-on-chip context

Authors:
Erno Salminen;Tero Kangas;Vesa Lahtinen;Jouni Riihimäki;Kimmo Kuusilinna;Timo D. Hämäläinen
Affiliations:
Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, FIN-33101 Tampere, Finland;Nokia Technology Platforms, Tampere, Finland;Nokia Technology Platforms, Tampere, Finland;Nokia Technology Platforms, Tampere, Finland;Nokia Research Center, Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, FIN-33101 Tampere, Finland
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2007

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Abstract

The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of the network depends heavily on the application and therefore six test cases with multiple parameter values are used. Furthermore, two versions of each network topology are compared. The results show that hierarchical bus scales well to large number of agents and offers a good performance and area trade-off although it has smaller aggregate bandwidth and area than mesh. Hierarchical HIBI bus achieves runtimes comparable to 2-dimensional cut-through mesh with about 50% smaller network logic. However, depending on the test case, the runtime can be reduced by 20-50% when wider bus links are utilized.