An architecture and compiler for scalable on-chip communication

  • Authors:

  • Jian Liang;Andrew Laffely;Sriram Srinivasan;Russell Tessier

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;U.S. Air Force, Hanscom AFB, MA;Advanced Micro Devices, Austin, TX;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2004

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Abstract

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-µm technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.