System-on-a-Chip Bus Architecture for Embedded Applications

Authors:
Affiliations:
Venue:
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Year:
1999

Citing 0
Cited 3

Powering networks on chips: energy-efficient and reliable interconnect design for SoCs

Proceedings of the 14th international symposium on Systems synthesis
An architecture and compiler for scalable on-chip communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SIMPPL: an adaptable SoC framework using a programmable controller IP interface to facilitate design reuse

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Increasing levels of on chip system integration means that more functional units need to be interconnected. To limit design effort and to allow for future reuse, this interconnection should be kept as simple and generic as possible. The need to limit clock cycle times and power consumption means that bus capacitance must be as low as possible. This can be done effectively by partitioning functional units onto discrete bus connections that are joined by bus bridges. This paper describes the evolution of ARM system chip architectures of steadily increasing complexity and details a state-of-the-art design.