Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A New Design Cost Model For The 2001 Itrs
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost-driven 3D integration with interconnect layers
Proceedings of the 47th Design Automation Conference
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ILP-based inter-die routing for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Reuse of existing designs is one of the most effective means for cost reduction. Three-dimensional (3D) stacking technology makes possible reuse of dies in 3D stack. GNet - a 3D architecture for reusing generic network service dies - is herein proposed to construct a network-on-chip (NoC) by virtue of exploiting reuse of known good dies (KGDs). In GNet, generic network service dies (GNSDs) are KGDs that integrate several networks and can be directly used to bond with other dies in 3D stack. Flexible and configurable design of GNet makes it suitable to requirements in various application circumstances. A comprehensive cost model, which combines the design cost model, reuse model and fabrication model, is introduced to evaluate different architectures from the design phase to the fabrication phase. Experiments show that GNet is more cost efficient than the general 3D implementations.