Data networks
A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Self-Similar Network Traffic and Performance Evaluation
Self-Similar Network Traffic and Performance Evaluation
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Delay Model for Router Microarchitectures
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
DRIL: Dynamically Reduced Message Injection Limitation Mechanism for Wormhole Networks
ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
Global Reactive Congestion Control in Multicomputer Networks
HIPC '98 Proceedings of the Fifth International Conference on High Performance Computing
Self-Tuned Congestion Control for Multiprocessor Networks
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A predictive flow control scheme for efficient network utilization and QoS
IEEE/ACM Transactions on Networking (TON)
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A Family of Mechanisms for Congestion Control in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A path-load based adaptive routing algorithm for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Proceedings of the 4th International Workshop on Network on Chip Architectures
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An analytical model for on-chip interconnects in multimedia embedded systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Networks-on-Chip (NoC) communication architectures have emerged recently as a scalable solution to on-chip communication problems. While the NoC architectures may offer higher bandwidth compared to traditional bus-based communication, their performance can degrade significantly in the absence of effective flow control algorithms. Unfortunately, flow control algorithms developed for macronetworks, either rely on local information, or suffer from large communication overhead and unpredictable delays. Hence, using them in the NoC context is problematic at best. For this reason, we propose a predictive closed-loop flow control mechanism and make the following contributions: First, we develop traffic source and router models specifically targeted to NoCs. Then, we utilize these models to predict the possible congestion in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network. We also illustrate the proposed traffic source model and the applicability of the proposed flow controller to actual designs using real NoC implementations. Finally, simulations and experimental study using our FPGA prototype show that the proposed controller delivers a better performance compared to the traditional switch-to-switch flow control algorithms under various real and synthetic traffic patterns.