Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data locality enhancement for CMPs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A topology design customization approach for STNoC
Proceedings of the 2nd international conference on Nano-Networks
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Yield enhancement by robust application-specific mapping on Network-on-Chips
Proceedings of the 2nd International Workshop on Network on Chip Architectures
The era of many-modules SoC: revisiting the NoC mapping problem
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Designing heterogeneous embedded network-on-chip platforms with users in mind
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes
Proceedings of the Conference on Design, Automation and Test in Europe
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture
Proceedings of the Third International Workshop on Network on Chip Architectures
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Studying inter-core data reuse in multicores
Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Studying inter-core data reuse in multicores
ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
A data layout optimization framework for NUCA-based multicores
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Neighborhood-aware data locality optimization for NoC-based multicores
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping
Microprocessors & Microsystems
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 21st International conference on Real-Time Networks and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, the approach is an efficient and accurate way to obtain the Pareto mappings that optimize performance and power consumption. Integration of the approach in an exploration framework with a kernel based on an event-driven trace-based simulator makes it possible to take account of important dynamic effects that have a great impact on mapping. Validation on both synthesized traffic and real applications (an MPEG-2 encoder/decoder system) confirms the efficiency, accuracy and scalability of the approach.