Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
Journal of the ACM (JACM)
A Traffic-Balanced Adaptive Wormhole Routing Scheme for Two-Dimensional Meshes
IEEE Transactions on Computers
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Performance tuning of adaptive wormhole routing through selection function choice
Journal of Parallel and Distributed Computing
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Static virtual channel allocation in oblivious routing
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we demonstrate that it is possible to design highly efficient application specific routing algorithms which distribute traffic more uniformly by using information regarding applications communication behavior (communication topology and communication bandwidth). We use off-line analysis to estimate expected load on various links in the network. The result of this analysis is used along with the available routing adaptivity in each router to distribute less traffic to links and paths which are expected to be congested. The methodology for Application Specific Routing Algorithms (APSRA) is extended to incorporate these features to design highly adaptive deadlock free routing algorithms which also distribute traffic more uniformly and reduce network congestion. We show that the number of congested links (links exceeding threshold bandwidth) is reduced by up to 100% with this extension. Significant reduction in average delay is also obtained for both synthetic (up to 25%) as well as a real application (12.5%) communication traffic with this extension to APSRA. We discuss architectural implications and area overhead of our approach on the design of a table based NoC router.