SystemC: methodologies and applications
SystemC: methodologies and applications
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Rapid Prototyping of NoC Architectures from a SystemC Specification
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predicting the performance of application-specific NoCs implemented on FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
SOC'09 Proceedings of the 11th international conference on System-on-chip
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
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Network-on-Chip (NoC) topology synthesis problem targets to generate NoC topology for multiple system design objectives such as performance and area. A multi-objective NoC synthesis and prototyping framework based on FPGA platform is proposed to design application specific NoC. Using the multi-objective algorithm NSGAII, the workflow aims to supply Pareto solutions for the multiple design objectives, rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. This multi-objective NoC synthesis is ensured by our complete TLM and RTL levels design framework. All the routers in the NoC library are synthesized for RTL implementation, and the area utilization information is used for hardware resource estimation at the high level NoC synthesis step. The system performances are obtained by SystemC TLM simulation with traffic defined in the core graph. After the high level NoC synthesis, the final selected Pareto solutions are generated and prototyped on FPGA platform with RTL traffic generators with same configurations as TLM level. Our multi-objective framework aims to provide a bridge from high level model to FPGA execution for accurate NoC design. Experiments on multimedia benchmark applications demonstrate the efficiency of this method.