A study on video browsing strategies
A study on video browsing strategies
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
An Automated Design Flow for NoC-based MPSoCs on FPGA
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
The RLOC is dead - long live the RLOC
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Modern FPGAs are able to implement complex systems such as Systems-on-Chips (SoCs) and Networks-on-Chips (NoCs). Appropriate NoC topology choices for ASICs have been investigated and typically topologies that can be easily mapped to a two-dimensional fabric are used to reduce chip area and ensure electrical characteristics. However, for FPGAs, each device's size and routing fabric are fixed. Since these resources exist independent of use, the choice of topology is only limited by the performance of the NoC itself. In this work, we investigate how topology characteristics impact a NoC's performance on an FPGA. From this analysis, we have created an analytical model that describes the maximum operating frequency of a NoC as a function of the topology's network parameters. This model is in the form of a simple equation that is accurate to within 4.68% across a range of topologies, chip sizes, and device families. It demonstrates how an FPGA's prefabricated routing interconnect provides increased freedom in the selection of application-specific topologies. Furthermore, it can also be used by designers for topology design space exploration before implementation.