Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Higher-Order and Symbolic Computation
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Map-reduce as a Programming Model for Custom Computing Machines
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Streams on wires: a query compiler for FPGAs
Proceedings of the VLDB Endowment
Proceedings of the VLDB Endowment
Predicting the performance of application-specific NoCs implemented on FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
FPMR: MapReduce framework on FPGA
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Programmable data dependencies and placements
DAMP '12 Proceedings of the 7th workshop on Declarative aspects and applications of multicore programming
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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Are user specified layout constraints of significant value anymore? Certainly in the past the use of the RLOC layout constraint for Xilinx FPGAs was essential for achieving the best possible performance for many kinds of highly structured designs. However, have CAD tools evolved to the point where they can always compute layouts as good as (if not better than) humans? Or has the introduction of on-chip hard cores, which create an irregular 2D surface for layouts, made layout specification impractical? Or has the varying pitch and types of combinational logic blocks (CLBs) made it intractable to produce layout descriptions that are portable across architectures? We show that the use of layout constraints still delivers a large performance gain for Xilinx's recent Virtex-6 family of FPGAs. The performance gain is sometime large enough to accommodate a reduction of two speed grades.