Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Introducing Core-Based System Design
IEEE Design & Test
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architectural descriptions for FPGA circuits
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
The RLOC is dead - long live the RLOC
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
Optimizing Xilinx designs through primitive instantiation
Proceedings of the 7th FPGAworld Conference
Programmable data dependencies and placements
DAMP '12 Proceedings of the 7th workshop on Declarative aspects and applications of multicore programming
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“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realized on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound effect on custom computing machines, which can be more easily, targeted from high-level specification languages like Handle-C and JHDL without requiring clumsy layout information to be accommodated at the language level.