Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Formal Methods in System Design
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
An integrated system for developing regular array designs
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Dynamically Reconfigurable Cores
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Framework for Developing Parameterised FPGA Libraries
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Automated field-programmable compute accelerator design using partial evaluation
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Architectural descriptions for FPGA circuits
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A declarative approach to incremental custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
| Hi-index | 0.00 |
Placement information is useful in producing efficient circuit layout, especially for hardware libraries or for run-time reconfigurable designs. Relative placement information enables control of circuit layout at a higher level of abstraction than placement information in the form of explicit coordinates. We present a functional specification of a procedure for compiling programs with relative placement information in Pebble, a simple language based on Structural VHDL, into programs with explicit placement coordinate information. This procedure includes source-level transformation for compiling into descriptions that support conditional compilation based on symbolic placement constraints, a feature essential for parametrised library elements. Partial evaluation is used to optimise a description using relative placement to improve its size and speed. We illustrate our approach using a DES encryption design, which results in a 60% reduction in area and a 6% improvement in speed.