A systolic LRU processor and its top-down development
Science of Computer Programming
An introduction to functional programming
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Systematic serialisation of array-based architectures
Integration, the VLSI Journal - Special issue on algorithms and architectures
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Parameterized convolution filtering in an FPGA
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Tools to speed FPGA development
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The priority queue as an example of hardware/software codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Towards a declarative framework for hardware-software codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Formal Methods in System Design
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Bandwidth Management with a Reconfigurable Data Cache
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Serialising heterogeneous and non-factorisable processor arrays
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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Abstract: Incremental methods can be used to produce implementations rapidly and to facilitate multi-level design optimisation. This paper describes a declarative framework, based on the language Ruby, that supports incremental design and validation of custom computers. The key elements of the approach include parameterised descriptions, design transformation and data refinement. Several priority queue designs are employed to illustrate our techniques and the computer-based tools; we also present the use of our framework in producing a priority queue implementation using Algotronix CAL devices.