Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Techniques for FPGA implementation of video compression systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Data-parallel C on a reconfigurable logic array
The Journal of Supercomputing - Special issue on field programmable gate arrays
Dynamic IPC/clock rate optimization
Proceedings of the 25th annual international symposium on Computer architecture
A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Application-specific memory management for embedded systems using software-controlled caches
Proceedings of the 37th Annual Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
A stream compiler for communication-exposed architectures
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Proceedings of the 30th annual international symposium on Computer architecture
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A declarative approach to incremental custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Merrimac: Supercomputing with Streams
Proceedings of the 2003 ACM/IEEE conference on Supercomputing
CoRAM: an in-fabric memory architecture for FPGA-based computing
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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With ever larger FPGA devices, hardware engineers are increasingly relying on automated tools to generate complex designs. However, relatively little attention has focused on automatically generating components of the memory hierarchy. Conventional cache research (despite its extensive study) rarely offers designs that map well to FPGAs. Here we propose an approach that uses compiler technology to analyze an application's predominant array access patterns and then generates a data cache customized for the application. The generic Reconfigurable Data Cache component and the technique used to automatically configure it are described. To demonstrate the feasibility of the proposed approach, a prototype has been implemented. We use the convolution as a representative multimedia operation, and show the benefit of the Reconfigurable Data Cache. Even though the computational structure for convolution is easy to generate automatically (from high-level source code), the resulting design alone is memory-bound and not faster than a comparable microprocessor. However, with the addition of the customized Reconfigurable Data Cache, the resulting system runs 5脳 faster and outperforms the reference microprocessor.