Techniques for FPGA implementation of video compression systems

Authors:
Brian Schoner;John Villasenor;Steve Molloy;Rajeev Jain
Affiliations:
Department of Electrical Engineering, University of California, Los Angeles, California;Department of Electrical Engineering, University of California, Los Angeles, California;Department of Electrical Engineering, University of California, Los Angeles, California;Department of Electrical Engineering, University of California, Los Angeles, California
Venue:
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Year:
1995

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Abstract

Real-time video compression is a challenging subject for FPGA implementation because it typically has a large computational complexity and requires high data throughput. Previous implementations have used parallel banks of FPGAs or DSPs to meet these requirements. Using design techniques that maximize FPGA utilization, we have implemented two video compression systems, each of which uses a single FPGA. In this first system, algorithmic optimizations are made to create a low-complexity implementation that exploits the in-system programmability of the FPGA. This low-complexity implementation performs well, but is limited to a single compression algorithm. In the second system, the FPGA is augmented with an external, low-complexity, video signal processor (VSP) This combination of ASIC and FPGA is flexible enough to implement four common compression algorithms, and powerful enough to execute them in real time.