RASP: a general logic synthesis system for SRAM-based FPGAs

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Partially-dependent functional decomposition with applications in FPGA synthesis and mapping

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference

Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Technology mapping for FPGAs with embedded memory blocks

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Delay-optimal technology mapping for FPGAs with heterogeneous LUTs

DAC '98 Proceedings of the 35th annual Design Automation Conference

Technology mapping for k/m-macrocell based FPGAs

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Synthesis for FPGAs with embedded memory blocks

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Simultaneous logic decomposition with technology mapping in FPGA designs

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays

Performance-driven multi-level clustering with application to hierarchical FPGA mapping

Proceedings of the 38th annual Design Automation Conference

SPFD-based global rewiring

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Architecture evaluation for power-efficient FPGAs

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

A new enhanced SPFD rewiring algorithm

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

FPGA technology mapping: a study of optimality

Proceedings of the 42nd annual Design Automation Conference

Optimality study of logic synthesis for LUT-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Clustering techniques for coarse-grained, antifuse FPGAs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Mapping for better than worst-case delays in LUT-based FPGA designs

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Area and delay trade-offs in the circuit and architecture design of FPGAs

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs

Proceedings of the 45th annual Design Automation Conference

Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

On K-LUT based FPGA optimum delay and optimal area mapping

MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering

Global delay optimization using structural choices

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Reconfigurable PLA Architecture for Nanomagnet Logic

ACM Journal on Emerging Technologies in Computing Systems (JETC)

FPGA logic synthesis using quantified boolean satisfiability

SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing

Power dissipation impact of the technology mapping synthesis on look-up table architectures

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Analyzing System-Level Information’s Correlation to FPGA Placement

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Towards interconnect-adaptive packing for FPGAs

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

From design to design automation

Proceedings of the 2014 on International symposium on physical design