Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Journal of the ACM (JACM)
Performance-driven multi-level clustering with application to hierarchical FPGA mapping
Proceedings of the 38th annual Design Automation Conference
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Clustering techniques for coarse-grained, antifuse FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computing the area versus delay trade-off curves in technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-optimal clustering targeting low-power VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best cluster starting from primary outputs moving backward in the circuit based on these curves. Experimental results show 16% and 20% reduction in dynamic and leakage power dissipation with 18% area reduction compared to the results of clustering without the replication prediction.