DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance-driven multi-level clustering with application to hierarchical FPGA mapping
Proceedings of the 38th annual Design Automation Conference
Sequential circuit synthesis at the gate level
Sequential circuit synthesis at the gate level
Clustering techniques for coarse-grained, antifuse FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We present a new synthesis flow for anti-fuse based FPGAs with multiple-output logic cells. The flow consists of two steps: mapping and packing. The mapper finds mapping solutions using a dynamic programming-based approach that finds the best match at each node of the decomposed target circuit. After this mapping step is completed, the resulting netlist of cells in optimally packed into net list of logic cells by using a multi-dimensional coin change problem formulation which is again solved by a dynamic programming based approach. Experimental results for Quicklogic's pASIC3 logic family are provided to assess the effectiveness of the proposed mapping and packing techniques.