Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exploring technology alternatives for nano-scale FPGA interconnects
Proceedings of the 42nd annual Design Automation Conference
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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This article describes a novel computing architecture organization based on nanoscale logic cells. We propose the use of a cluster of matrix arrangements of cells. In order to interconnect such fine-grained logic cells within a matrix, conventional techniques are not suitable due to a large interconnect overhead. Therefore, we propose the use of static and incomplete interconnect topologies to create matrices of cells. We also propose a method to map functions onto such architectures. We then explore the main parameters of the structure (size of matrices and interconnect topologies) and their impact on the main performance metrics (packing efficiency, speed, and fault tolerance). A cluster packing method also allows the evaluation of the number of matrices used by complex functions and the fill factor for various matrix sizes. The analyses show that this approach is particularly suited for matrices of 16 cells interconnected by modified omega networks. We can conclude that this architecture could improve the scalability of traditional FPGAs by a factor of 8.5.