SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Efficient power co-estimation techniques for system-on-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Memory system energy (poster session): influence of hardware-software optimizations
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Proceedings of the 39th annual Design Automation Conference
ICS '02 Proceedings of the 16th international conference on Supercomputing
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
IEEE Micro
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliable communication in systems on chips
Proceedings of the 41st annual Design Automation Conference
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
DNCOCO'07 Proceedings of the 9th WSEAS International Conference on Data Networks, Communications, Computers
A new selection policy for adaptive routing in network on chip
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
Computers and Electrical Engineering
Computers and Electrical Engineering
Reducing the associativity and size of step caches in CRCW operation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
Multi-CMP system with data communication on the fly
The Journal of Supercomputing
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
Designing on-chip network based on optimal latency criteria
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Data transfers on the fly for hierarchical systems of chip multi-processors
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
Non-minimal, turn-model based NoC routing
Microprocessors & Microsystems
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Some current and most future systems-on-chips use and will use network architectures/protocols to implement on-chip communication. On-chip networks borrow features and design methods from those used in parallel computing clusters and computer system area networks. They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements). In this paper, we analyze different routing schemes for packetized on-chip communication on a mesh network architecture, with particular emphasis on specific benefits and limitations of silicon VLSI implementations. A contention-look-ahead on-chip routing scheme is proposed. It reduces the network delay with significantly smaller buffer requirement. We further show that in the on-chip multiprocessor systems, both the instruction execution inside node processors, as well as data transaction between different processing elements, are greatly affected by the packetized dataflows that are transported on the on-chip networks. Different packetization schemes affect the performance and power consumption of multiprocessor systems. Our analysis is also quantified by the network/multiprocessor co-simulation benchmark results.