Performance Analysis of Buffering Schemes in Wormhole Routers
IEEE Transactions on Computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
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This paper explores efficient buffer architectures for toplevel mesh routers in HiNoC, a hierarchical Network-on-Chip. Multiple approaches to buffering are discussed and a size-performance comparison of synthesis results is performed. Among the possible buffer architectures, output buffering and middle buffering are examined carefully by evaluating the impact of variations in significant parameters on the router's overall area. This is done by synthesizing a generic design onto a FPGA. Eventually, middle buffering is identified as best buffer architecture and the influence of the aforementioned parameters on the area requirements is formalized.