Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Specification and design of embedded systems
Specification and design of embedded systems
The design of mixed hardware/software systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Proceedings of the 6th international workshop on Hardware/software codesign
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the tenth international symposium on Hardware/software codesign
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Interconnect IP Node for Future System-on-Chip Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
High-level Architectural Simulation of the Torus Routing Chip
IVC '97 Proceedings of the 1997 IEEE International Verilog HDL Conference (IVC '97)
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal
Computers and Electrical Engineering
Hardware implementations of software programs based on hierarchical finite state machine models
Computers and Electrical Engineering
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In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally we will summarize the concept combined with an outlook on further investigations.