PRISC: programmable reduced instruction set computers
PRISC: programmable reduced instruction set computers
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Compiling Esterel into sequential code
Proceedings of the 37th Annual Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Efficient compilation of ESTEREL for real-time embedded systems
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Logic optimization and code generation for embedded control applications
Proceedings of the ninth international symposium on Hardware/software codesign
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
A software development tool chain for a reconfigurable processor
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Don't cares and multi-valued logic network minimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Garp Architecture and C Compiler
Computer
PRISC Software Acceleration Techniques
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Adaptive explicitly parallel instruction computing
Adaptive explicitly parallel instruction computing
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Using reconfigurability to achieve real-time profiling for hardware/software codesign
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
An overview of embedded system design education at berkeley
ACM Transactions on Embedded Computing Systems (TECS)
Embedded system education: a new paradigm for engineering schools?
ACM SIGBED Review - Special issue: The first workshop on embedded system education (WESE)
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Algorithms for the automatic extension of an instruction-set
Proceedings of the Conference on Design, Automation and Test in Europe
Better by a HAIR: hardware-amenable Internet routing
Computer Networks: The International Journal of Computer and Telecommunications Networking
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A framework for compiler driven design space exploration for embedded system customization
ASIAN'04 Proceedings of the 9th Asian Computing Science conference on Advances in Computer Science: dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday
The Journal of Supercomputing
The q2 profiling framework: driving application mapping for heterogeneous reconfigurable platforms
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Communication-aware HW/SW co-design for heterogeneous multicore platforms
Proceedings of the 2012 Workshop on Dynamic Analysis
Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
Refinement of UML/MARTE models for the design of networked embedded systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The hw/sw codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (Extended Finite State Machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementations that best utilize this architecture. Encouraging preliminary results are shown for automotive electronic control examples.