Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An integer programming approach to instruction implementation method selection problem
EURO-DAC '92 Proceedings of the conference on European design automation
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Graph Isomorphism and Identification Matrices: Parallel Algorithms
IEEE Transactions on Parallel and Distributed Systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Solving covering problems using LPR-based lower bounds
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new viewpoint on code generation for directed acyclic graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Automatic detection of recurring operation patterns
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications
Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PRISC Software Acceleration Techniques
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the tenth international symposium on Hardware/software codesign
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automatic design of computer instruction sets
Automatic design of computer instruction sets
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Removing communications in clustered microarchitectures through instruction replication
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Effective bounding techniques for solving unate and binate covering problems
Proceedings of the 42nd annual Design Automation Conference
An integer linear programming approach for identifying instruction-set extensions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Compiling for automatically generated instruction set extensions
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Designing tightly-coupled extension units for the STxP70 processor
Proceedings of the Conference on Design, Automation and Test in Europe
Loop acceleration exploration for ASIP architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature.