An integer programming approach to instruction implementation method selection problem
EURO-DAC '92 Proceedings of the conference on European design automation
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Using register-transfer paths in code generation for heterogeneous memory-register architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of reusable DSP cores based on multiple behaviors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Time-constrained code compaction for DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
An ASIP instruction set optimization algorithm with functional module sharing constraint
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multiple behavior module synthesis based on selective groupings
Proceedings of the conference on Design, automation and test in Europe
Introduction to Algorithms
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Introduction of local memory elements in instruction set extensions
Proceedings of the 41st annual Design Automation Conference
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
IEEE Transactions on Computers
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
A quantitative study and estimation models for extensible instructions in embedded processors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Polynomial-time subgraph enumeration for automated instruction set extension
Proceedings of the conference on Design, automation and test in Europe
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A scalable synthesis methodology for application-specific processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A polynomial-time custom instruction identification algorithm based on dynamic programming
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ISNN'13 Proceedings of the 10th international conference on Advances in Neural Networks - Volume Part I
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Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, while the previous state-of-the-art approaches generate only the single-cycle instructions or just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applied to the case that instructions are predefined. Experimental results on real applications show that various given constraints can be met by the generated set of application specific instructions without attaching special hardware accelerators.