Automatic application-specific microarchitecture reconfiguration

  • Authors:

  • Shobana Padmanabhan;Ron K. Cytron;Roger D. Chamberlain;John W. Lockwood

  • Affiliations:

  • Dept. of Computer Science and Engineering, Washington University, St. Louis;Dept. of Computer Science and Engineering, Washington University, St. Louis;Dept. of Computer Science and Engineering, Washington University, St. Louis;Dept. of Computer Science and Engineering, Washington University, St. Louis

  • Venue:
  • IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
  • Year:
  • 2006

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Abstract

Applications for constrained embedded systems are subject to strict time constraints and restrictive resource utilization. With soft core processors, application developers can customize the processor for their application, constrained by resources but aimed at high application performance. With such freedom in the design space of the processor, however, comes complexity. We present here an automatic optimization technique that helps the developers with the processor microarchitecture customization. A naive approach exploring all possible configurations is exponential with the number of parameters and hence is clearly infeasible, even with only tens of reconfigurable parameters. Instead, our approach runs in time that is linear with the number of parameter values, based on an assumption of parameter independence. This makes the approach feasible and scalable. For the dimensions that we customize, namely application runtime and hardware resources, we formulate their costs as a constrained binary integer nonlinear optimization program. Though the results are not guaranteed to be optimal, we find they are nearoptimal in practice. Our technique itself is general and can be applied to other design-space exploration problems.