Evolving algebras 1993: Lipari guide
Specification and validation methods
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A joined architecture/compiler design environment for ASIPs
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Design space characterization for architecture/compiler co-exploration
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Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Formal aspects of and development environments for Montages
Algebraic'97 Proceedings of the 2nd international conference on Theory and Practice of Algebraic Specifications
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Feedback driven instruction-set extension
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the conference on Design, automation and test in Europe
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ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program.In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark.