System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Compiler-directed customization of ASIP cores
Proceedings of the tenth international symposium on Hardware/software codesign
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Low-power embedded DSP core for communication systems
EURASIP Journal on Applied Signal Processing
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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Although a number of DSP cores are currently available for application-specific IC design, they typically offer limited possibilities for customizing the core itself. In our approach, a parameterized and extensible DSP core was designed. This new breed of licensable DSP cores offers a great deal of flexibility for the system engineers in their attempt to find the optimum cost/performance ratio for a given application. Among variable data word width and the number of registers, a wide range of other core parameters can be specified. Moreover, the core features an extensible instruction set which supports execution of special operations in the datapath or in the off-core custom hardware. With the extension instructions and additional circuitry, it is possible to fine-tune the instruction set for specific needs of the modern signal processing applications. In this article, we present the flexible DSP core architecture and the software development tools supporting design space exploration. Finally, the benefits of this approach are illustrated with an application example, in which the algorithms of the GSM full rate speech coding were implemented with four different core configurations.