Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
Increasing design quality and engineering productivity through design reuse
DAC '93 Proceedings of the 30th international Design Automation Conference
An approach for redesigning in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Datapath optimization using feedback
EURO-DAC '91 Proceedings of the conference on European design automation
Hardware/software partitioning for multi-function systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific instructions for embedded DSP software
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
Multiple behavior module synthesis based on selective groupings
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
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Design with cores has become popular recently because it can decrease the design time and ease the complexity of the design process. This paper presents a new method for the design of DSP cores based on multiple behaviors. This method uses redesign technique based on reallocation transformations to extract those RTL components in an initial RTL structure which are highly reusable and uses them to construct a DSP core. Experimental results are provided to illustrate the high reusability of core, extracted from given behaviors, when it accommodates new behaviors.