An integer programming approach to instruction implementation method selection problem
EURO-DAC '92 Proceedings of the conference on European design automation
Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of reusable DSP cores based on multiple behaviors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An ASIP instruction set optimization algorithm with functional module sharing constraint
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
An Integrated Design Environment for Application Specific Integrated Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Synthesis of application specific instructions for embedded DSP software
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
| Hi-index | 0.00 |
In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented, the previous methods scheduled each of them sequentially, and implemented them as a single module. Though the method is appropriate for sharing the functional units, it ignored the following two aspects: 1) different interconnection patterns among DFGs can increase the interconnection area and delay of the critical path, 2) the sequential scheduling of DFGs has a difficulty in considering the effects on the other DFGs not scheduled yet. We show an efficient way to solve the problems using a selective grouping method and the extensions of the traditional scheduling methods. The experimentation reveals that the result obtained by the proposed method is better to reduce interconnection area and to meet the timing constraints than those obtained by the previous methods.