Synthesis of reusable DSP cores based on multiple behaviors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Computers
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Reconfigurable parallel inner product processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Uniformization of Affine Dependance Programs for Parallel Embedded System Design
ICPP '02 Proceedings of the 2001 International Conference on Parallel Processing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A high-speed energy-efficient 64-bit reconfigurable binary adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Large Scale Adaptable Multiplier for Cryptographic Applications
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Integration, the VLSI Journal
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers
Fine- and Coarse-Grain Reconfigurable Computing
Fine- and Coarse-Grain Reconfigurable Computing
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A high-performance data path for synthesizing DSP kernels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided.